1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and its manufacturing method, and more particularly to a method for enhancing the performance, increasing the degree of integration, and improving the yield.
2. Description of the Related Art
Flash memories excel in portability and shock resistance. Further, they can be electrically erased at a time. In recent years, therefore, they have been increasingly demanded as a filing device for use with mobile personal computers, digital still cameras, video cameras, and other small-size, portable information devices. Reducing the bit cost by decreasing the memory cell region and enhancing the programming speed for supporting a quick content download are essential for flash memory market expansion. Some memory cell methods for achieving such a purpose are now proposed. For example, a virtual grounding type memory cell based on a three-layer polysilicon gate is disclosed (refer to JP-A No. 028428/2001 or JP-A No. 085541/2001). As shown in FIG. 15, this memory cell comprises a floating gate 204, which serves as a first gate, a control gate 205, which serves as a second gate, and a third gate 206. The memory cell comprises a well 202 in a silicon substrate 201, a source in the well, drain diffusion layer regions 203, 203′, and a first gate composed of polysilicon film formed on the well. The third gate incorporates the functionality of either an erase gate or a split channel control gate. Dielectric films 207, 208, 209, 210, 211 are used to separate polysilicon gates 204, 205, 206 and separate the well 202 from the polysilicon gates. The control gate 205 is connected in the row direction to constitute a word line. The source and drain diffusion layer regions 203, 203′ are of a virtual grounding type, which shares an adjacent memory cell diffusion layer. This reduces the pitch in the row direction. The third gate 206 is perpendicular to a channel and positioned perpendicularly to the word line 205. When a programming operation is to be performed, an independent positive voltage is applied to the word line 205, drain 203, and third gate 206, and the well 202 and source 203′ are set at 0 V. Hot electrons are then generated on a channel at a boundary between the third gate and floating gate and introduced into the floating gate 204. This results in an increase in the memory cell threshold voltage. When an erasing operation is to be performed, a positive voltage is applied to the third gate 206, and a negative voltage is applied to the word line 205. The source 203′, drain 203, and well 202 are set at 0 V. Electrons are then emitted from the floating gate 204 to the third gate 206 so that the threshold voltage decreases. A negative voltage is applied to the word line 205. The third gate 206, source 203′, drain 203, and well 202 are set at 0 V. Electrons are then emitted from the floating gate 204 to the well 202 so that the threshold voltage decreases. The memory cell transistor threshold voltage is varied in this manner to distinguish between the information values “0” and “1”.
However, new tasks arise when an attempt is made to increase the capacity of the above nonvolatile semiconductor memory device.
The first task is to decrease the internal operating voltage for programming or erasing a memory cell. This task is particularly evident when an attempt is made to erase a memory cell. As regards a flash memory, the following equation generally expresses the relationship between the control gate voltage Vcg and floating gate Vfg:Vfg=Vcg×C2/(C1+C2+Cag+Cfg)  Equation (1)                where C1 is the capacity of dielectric film (tunnel dielectric film) between the floating gate and the Si substrate, C2 is the capacity of dielectric film (interpoly dielectrics) between the floating gate and the control gate, Cag is the capacity of dielectric film between the floating gate and the third gate, and Cfg is the capacity of dielectric film between floating gates under an adjacent word line. The value C2/(C1+C2+Cag+Cfg) is called a coupling ratio. To ensure that a voltage applied to the control gate is efficiently transmitted to the floating gate for the purpose of performing a programming/erasing operation, it is essential that the coupling ratio be increased. To achieve this purpose, it is important to (1) increase the capacity of interpoly dielectrics C2, (2) reduce Cag by increasing the thickness of film between the third gate and floating gate, and (3) provide the floating gate with a U- or fin-shaped cross section in order to reduce the cross-sectional area of the floating gate and decrease the capacity of dielectric film Cfg between opposing floating gates. To increase C2, it is necessary to increase the floating gate surface area. In the above publicly known example, however, it is difficult to decrease the operating voltage because the floating gate 204 has a small surface area. This problem is particularly crucial for an erasing operation that is performed by applying a high voltage to the dielectric film 210 between the floating gate and Si substrate and emitting electrons accumulated in the floating gate toward the substrate due to tunneling. For a multilevel flash memory, which stores two bits of data per memory cell, the memory cell threshold voltage difference between the programming state and erasing state needs to be great. It is essential that the coupling ratio be improved to reduce the programming/erasing time.        
The second task is to reduce deviation programming speed distribution and miniaturize the third gate. Various methods for forming a virtual grounding type memory cell with a three-layer polysilicon gate are stated in JP-A No. 085541/2001. In a certain method stated in JP-A No. 085541/2001, which forms a floating gate 204 after forming a third gate 206, a gate bird's beak is generated. More specifically, the lower end of the third gate 206, which is formed earlier, is oxidized when a tunnel dielectric film 210 is formed by means of thermal oxidation, so that the gate oxide film thickness increases.
The reason is that the gate oxide film for the lower end of the third gate is removed in a cleaning process for tunnel dielectric film formation. As a result, the lower end of the third gate polysilicon film is oxidized. The growth of the gate bird's beak varies the threshold voltage of a MOS transistor, which is formed by the third gate, so that deviation of programming distribution of memory cell increase. The increase in the memory cell programming speed deviation causes an increase in the number of verifications for judging whether a specified threshold level is reached by a multilevel flash memory. This results in an increase in the chip programming time. Further, when the gate oxide film thickness of the third gate increases due to the growth of the gate bird's beak, the punch-through immunity of the MOS transistor formed by the third gate decreases, making it difficult to reduce the gate length.
The third task is to miniaturize the word line. For high-density flash memories, the word line is generally patterned to the minimum dimensions for memory cell miniaturization. To achieve this purpose, it is necessary to provide an adequate focus margin in a lithography process for word line patterning. Consequently, the third task is to minimize the step coverage.
As described above, the development of a new nonvolatile semiconductor memory device and its manufacturing method has been called for in order to miniaturize a virtual grounding type memory cell based on a three-layer polysilicon gate and accomplish the tasks for performance enhancement.